The present invention relates to a semiconductor integrated circuit, and in particular to an improvement of a construction of a data line precharge power supply when data is transferred from memory cells to an output circuit on a semiconductor chip. The improvement can be effectively used in a dynamic random access memory (which will be referred to as "DRAM") and a static random access memory (which will be referred to as "SRAM").
Two kinds of precharge power supply systems for data lines have been proposed for SRAMs which use a data line amplifier formed of a differential amplifier of the current mirror type in order to increase an operation speed in many cases.
One of them is disclosed in "1985 ISSCC Technical Digest", p. 65, FIG. 1. This system uses N-MOS transistors and a power supply generating a potential Vcc for precharging the data lines.
A DRAM to which the above technique is applied will be described below as a first prior art with reference to FIG. 11. Prior to description of a function of a precharge circuit in the DRAM, general description will first be given on a whole circuit shown in FIG. 11. There are provided sense amplifier blocks BLKn, BLKm and BLKl (19, 20 and 21) into which the integrated circuit is divided. Although an internal configuration of only the sense amplifier block BLKn (19) is shown in the figure, these blocks 19, 20 and 21 have the same configuration. In the sense amplifier blocks BLKn, BLKm and BLKl (19, 20 and 21), a word line 15 is first controlled to read data of a memory cell 7 onto bit lines 2, and a power supply Vcc (32) and a ground potential Vss are supplied to common source lines SAP (17) and SAN (16), respectively, so that P-MOS and N-MOS sense amplifiers 8 and 9 of the flip-flop type latch the data on the bit lines 2. The data thus latched is read onto first data lines DQn and XDQn (1) via N-MOS transfer transistors (i.e., decode switch) (10) controlled by a column select line Yn (6) into which a signal AYp of a column address decoder 12 is input.
To the first data lines DQn and XDQn (1) are connected a precharge circuit 71 formed of N-MOS transistors for precharging the data lines DQn and XDQn (1), and a clamp circuit 70 formed of N-MOS transistors for clamping the potential at the low level of one of the data lines DQn and XDQn (1). The data read onto the first data lines DQn and XDQn (1) is detected and amplified by a differential amplifier 4 shown in FIG. 14(a) and FIG. 14(b), and further is read onto second data lines DB and XDB (3) via a switch 11 controlled by an address decoder 13. The second data lines DB and XDB (3) are precharged by a circuit similar to the precharge circuit 71, and the data is detected and amplified by an amplifier 5 similar to the differential amplifier 4, and ultimately is read externally by an output buffer 14.
The conventional precharge power supply system of the other type will now be described below. This technique uses P-MOS transistor as well as a power supply generating the potential Vcc for precharging data lines, as shown in "1992 ISSCC Technical Digest". p. 209, FIG. 1.
A second prior are which is a DRAM employing the above technique is shown in FIG. 13. For simplicity reasons, only difference with respect to the DRAM in FIG. 11 will be described below. The difference is that a precharge circuit 81 for the first data lines DQn and XDQn (1), a clamp circuit 80 for clamping the potential at the low level of one of the data lines 1, a precharge circuit 90 for the second data lines 3 and a latch circuit 91 each are formed of P-MOS transistors.
The inventors have specifically studied the operation of the first and second prior arts to find that these prior arts have the following advantages and disadvantages.
In the first prior art, since the precharge circuit 71 is formed of the N-MOS transistors, the potential precharging the first data lines 1 is equal to (Vcc-Vt) which is lower than the potential Vcc of the power supply 32 by a threshold voltage Vt of the N-MOS transistor. Meanwhile, in the second prior art, since the precharge circuit 81 is formed of the P-MOS transistors, the potential precharging the first data lines 1 is equal to the potential Vcc of the power supply 32 itself.
The amplifier shown in FIG. 14(a) and FIG. 14(b) in FIG. 14 is a generally used amplifier of the voltage detecting type. The sensitivity (sensitivity=output potential difference/input potential difference) of this amplifier is low with respect to a potential of the input data near the power supply potential Vcc of the power supply 32 as shown in FIG. 15, and generally attains a maximum value near the potential of Vcc/2. Accordingly, in the first prior art described above, the potential of the data lines 1 is precharged to the potential (Vcc-Vt) lower than the power supply voltage Vcc, so that the sensitivity can be high. However, in the second prior art described above, the low sensitivity of the amplifier cannot be avoided as long as it uses the amplifier of the voltage detecting type shown in FIG. 14(a) and FIG. 14(b).
Meanwhile, in the precharge potential generating system in the first prior art has the following disadvantage. FIGS. 12(a) and 12(b) show change of the potential of the data lines 1 which occurs due to negative bump of the power supply voltage Vcc, i.e., voltage drops thereof. If the power supply voltage Vcc does not change, transition of data on the data lines 1 can be performed in a time t1 after inverted data is transferred. However, if the power supply voltage Vcc drops after the transition, the clamp potential of the data line XDQn, which is at the low level at this point of time, lowers in accordance with lowering of the power supply voltage Vcc, but the potential of the data line DQn, 20 which is at the high level, cannot follow it and maintains the previous potential as shown in FIGS. 12(a) and 12(b), so that a large potential difference is caused in the data line pair DQn and XDQn. Consequently, when new inverted data is transferred, a long inversion time t2 is required, which may cause malfunction of an amplifier at a subsequent stage. The operation speed cannot be increased if this problem is to be overcome.
The aforementioned characteristics relating to the followability are presented by the following reasons. Both the clamp circuit 70 and decode switch 10 are formed of the N-MOS transistors. Due to this, for example, when one of the bit lines BL is kept at the power supply potential Vcc and the other bit line/BL is kept at the ground potential Vss, i.e., when the data lines DQn and XDQn are kept at the high and low levels, respectively, the N-MOS transistors forming the clamp circuit 70 and decode switch 10 present diode characteristics which cause current flow toward a low potential side, so that the data line XDQn, which is at the lower level at the time of voltage drop, is connected to the ground line via one of the N-MOS transistors of the decode switch 10 shown at a lower position in the figure and the bit line/BL as well as the N-MOS sense amplifier transistor 9, and lowers its potential in accordance with the fall of the power supply voltage Vcc. Meanwhile, in connection with the data line DQn, which is at the higher level at the time of the voltage drop of the power supply 32, a current path to the ground is disconnected by a diode formed of the N-MOS transistor of the decode switch 10 shown at the upper position in the figure, and further, it is electrically isolated from the power supply Vcc by the diode formed of the N-MOS transistor of the clamp circuit 70 shown at the upper position in the figure. For this reason, it can be considered that the potential of the data line DQn cannot follow the voltage drop. In the above description, the decode switch 10 is formed of the N-MOS transistors, so that the N-MOS transistors forming the clamp circuit 70 perform the diode function. Meanwhile, if the decode switch 10 were formed of P-MOS transistors, the P-MOS transistors forming the clamp circuit 70 would perform the diode function. Therefore, a disadvantage is caused if the transistors forming the clamp circuit 70 are of the same conductivity type as the transistors forming the decode switch 10.
The problem of the first prior art described above is not presented by the second prior art, because the power supply and the data lines in the second prior art are electrically connected together via P-MOS transistors 80, and hence the change in the power supply voltage Vcc can be followed.
Accordingly, the problem relating to operation stability of the circuit is caused if the first or second prior art is employed for data lines of recent memories having a large capacity and allowing fast operation.